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25AA02E48
2.5
Read Status Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘ 1 ’, the latch allows writes to the array, when set to a
The Read Status Register instruction ( RDSR ) provides
access to the STATUS register. See Figure 2-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
‘ 0 ’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
TABLE 2-2:
STATUS REGISTER
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
7 6 5 4 3 2 1
– – – – W/R W/R R
X X X X BP1 BP0 WEL
0
R
WIP
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25AA02E48 is busy with a write operation. When set to
a ‘ 1 ’, a write is in progress, when set to a ‘ 0 ’, no write
is in progress. This bit is read-only.
FIGURE 2-6:
CS
READ STATUS REGISTER TIMING SEQUENCE ( RDSR )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
SI
0
0
0
0
0
1
0
1
SO
High-Impedance
7
Data from STATUS register
6 5 4 3 2
1
0
DS22123B-page 10
? 2010 Microchip Technology Inc.
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